#include "stdio.h"
#include"cpu.h"

#ifndef __GNUC__
#pragma warning(disable : 4700)
#endif

int CCPU::exec_thumb( )
{

		switch(thumb_insn.code>>12)
		{
			
		case 0:
		// format 1:LSL/ LSR/ASR
			//insn_id=(thumb_insn.code&(1<<11))?THUMB_LSR:THUMB_LSL;
			__asm int 3;
			break;
		case 1:
			if((thumb_insn.code&(1<<11))==0)
			{
				;//insn_id=THUMB_ASR;
			__asm int 3;
			}
			else
			{
		// format 2:
				//insn_id=thumb_insn.insn_fmt2.op?THUMB_SUB:THUMB_ADD;
			}
			__asm int 3;
			break;
		// format 3:
		case 2:// MOV/ CMP/ADD/SUB
			//insn_id=(thumb_insn.code&(1<<11))?THUMB_MOV:THUMB_CMP;
			__asm int 3;
			break;
		case 3:
			//insn_id=(thumb_insn.code&(1<<11))?THUMB_SUB:THUMB_ADD;
			__asm int 3;
			break;
		case 4:
		     if((thumb_insn.code&(1<<11)))
			 {
		//Format 6: PC-relative load
				 //insn_id=THUMB_LDR;
				 __asm int 3;
			 }
			 else
		// Format 4: ALU operations
			if((thumb_insn.code&(1<<10))==0)
			{
				//insn_id=(INSN_ID)(thumb_insn.insn_fmt4.op+THUMB_AND);
				__asm int 3;
			}
		//Format 5: Hi register operations/branch exchange
			else
			{
				static INSN_ID  thumb_fmt5[]={
					THUMB_ADD,THUMB_CMP,THUMB_MOV,THUMB_BX
				};
				//insn_id=thumb_fmt5[thumb_insn.insn_fmt5.op];
				__asm int 3;
			}
			break;
		case 5:
			if((thumb_insn.code&(1<<9))==0)
			{
		//Format 7: load/store with register offset
				static INSN_ID  thumb_fmt7[]={
					THUMB_STR,THUMB_STRB,THUMB_LDR,THUMB_LDRB
				};
				// {L,B}
				//insn_id=thumb_fmt7[(thumb_insn.code>>10)&3];
				__asm int 3;
			}
			else
			{
		//Format 8: load/store sign-extended byte/halfword
				static INSN_ID  thumb_fmt8[]={
					THUMB_STRH,THUMB_LDRH,THUMB_LDSB,THUMB_LDSH
				};
				// {H,S}
				//insn_id=thumb_fmt8[(thumb_insn.code>>10)&3];
				__asm int 3;
			}
			break;
		case 6:
		case 7:
			{
		//Format 9: load/store with immediate offset
				static INSN_ID  thumb_fmt9[]={
					THUMB_STR,THUMB_LDR,THUMB_LDRB,THUMB_STRB
				};
				// {B,L}
				//insn_id=thumb_fmt9[(thumb_insn.code>>11)&3];
			}

			__asm int 3;
			break;
	
		case 8:
		//Format 10: load/store halfword
			//insn_id=(thumb_insn.code&(1<<11))?THUMB_STRH:THUMB_LDRH;
			__asm int 3;
			break;

		case 9:
		//Format 11: SP-relative load/store
			//insn_id=(thumb_insn.code&(1<<11))?THUMB_STR:THUMB_LDR;
			__asm int 3;
			break;
		case 10:
		//Format 12: load address
			//insn_id=THUMB_ADD;
			__asm int 3;
			break;

		case 11:
			if((thumb_insn.code&(1<<9))==0)
			{
		//Format 13: add offset to Stack Pointer
			//insn_id=THUMB_ADD;
				__asm int 3;
			}
			else
			{
		//Format 14: push/pop registers
				//insn_id=(thumb_insn.code&(1<<11))?THUMB_PUSH:THUMB_POP;
				__asm int 3;
			}
			break;
	
		case 12:
		//Format 15: multiple load/store
			//insn_id=(thumb_insn.code&(1<<11))?THUMB_STMIA:THUMB_LDMIA;
			__asm int 3;
			break;
		case 13:
		//Format 16: conditional branch
			if(thumb_insn.insn_fmt16.cond<0xe)
			{
				//insn_id=(INSN_ID)(THUMB_BEQ+thumb_insn.insn_fmt16.cond);
				__asm int 3;
			}
			else if(thumb_insn.insn_fmt16.cond==0xf)
			{
		//Format 17: software interrupt
				//insn_id=THUMB_SWI;
				__asm int 3;
			}
			else
			{
				__asm int 3;
				BUG(UD,__LINE__,__FILE__);
			}
			break;
		case 14:
		//Format 18: unconditional branch
			//insn_id=THUMB_B;
			__asm int 3;
			break;
		case 15:
		//Format 19: long branch with link
			//insn_id=THUMB_BL;
			__asm int 3;
			break;

		}


		return 0;
}
